Tabu Search Based Gate Leakage Optimization using DKCMOS Library in Architecture Synthesis

The gate-oxide (aka gate tunneling or gate) leakage due to quantum-mechanical direct tunneling of carriers across the gate dielectric of a device is a major source power dissipation for sub-65nm CMOS circuits. In this paper a high-level (aka architecture) synthesis algorithm is presented that simultaneously schedules operations and binds to modules for gate leakage optimization. The algorithm uses device-level gate leakage models for precharacterizing register-transfer level datapath component library. The algorithm minimizes the gate leakage for given resource and time constraints. The dual-K CMOS (DKCMOS) technology is used as a method for gate leakage power reduction in a data flow graph. The proposed algorithm is tested for several high-level synthesis benchmarks for two types of DKCMOS, SiO2-SiON and SiO2-Si3N4, for 45nm node. The experiments showed that gate leakage reduction in average 60% and 72% for SiO2-SiON and SiO2-Si3N4, respectively, could be achieved.